SACHEM Introduces Reveal Etch™ for TSV Silicon Etching

SACHEM Introduces Reveal Etch™ for TSV Silicon Etching

(Austin, Texas) Thursday April 24, 2015    SACHEM is announcing the release of Reveal Etch™, a wet chemistry designed to enable a single-step silicon etch/TSV reveal process. SACHEM developed the chemistry in its R&D center in Austin TX and demonstrated its performance in a Solid State‘s single-wafer processor, as part of the cohabitation between the two companies.

“SACHEM’s Reveal Etch™ chemistry works great with high etch rate, smooth surface finish, and very high SiO2 selectivity” stated Dr. Yongqiang Lu, Director of Electronic Application at SACHEM, Inc.

SACHEM’s Reveal Etch™ chemistry is designed for low cost-of-ownership TSV processing by providing a single-step, highly selective silicon etch process resulting in low silicon surface roughness and reduced sub-surface stress, eliminating the need for a separate CMP step. The combination of high-speed, low-surface roughness, and high selectivity make Reveal Etch™ a good candidate wherever precision silicon etching is required.

SSEC and SACHEM have worked on this chemistry and process since early 2013, presenting their findings at the 2014 IEEE Electronic Components and Technology Conference (ECTC 2014).  Click here to request a copy of the technical paper that was presented.

SACHEM has initiated manufacturing of the Reveal Etch™ product and is conducting customer sampling and evaluations with multiple partners developing 3D integration processes. “The success of any new product is a combination of great innovation and diligent focus on the cycles of learning that can only be achieved with strong customer engagements,” said Dr. Kevin McLaughlin, Global Electronic Materials Marketing Manager. “This combination is at the core of SACHEM’s business.”